Learn FPGA 1: Getting Started with edge spartan 7 fpga kit using Vivado Design Suite

How to Install Vivado & Create Your First FPGA Project | 100 Days of FPGA

How to Use IP Blocks in Vivado | Step-by-Step Guide to IP Integration in FPGA Design

design and simulate BRAM using IP configurator

Implementating the Design in Vivado and IO Pin Planning for Configurable FPGA.

Using Xilinx IP Cores Within Your Design

Vivado HLS demonstration C function to FPGA

Xilinx HLS #2: FPGA FIR Filter Design in C in 30 minutes (Vivado High Level Synthesis)

Lesson4：Vivado HLS设计流程 -- 实例演示（Xilinx）