The following tutorial, by Stuart Sutherland of Sutherland HDL, is an updated version of a paper presented at HDLCon in March 2000. It provides an overview of the changes in the Verilog-2001 standard.

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking ...

The conference's general chair is Karen Bartleson, director of interoperability, also of Synopsys. In addition, the company will deliver SystemVerilog tutorials and functional verification papers that ...