Design-Reuse

System Verilog + OVM: Mitigating Verification Challenges & Maximizing Reusability

Verification – has been becoming a nightmare for engineers with the increasing requirements and complexity of the design. Mitigating the complexity of a verification environment with the increasing ...
EDN

Comparing Verilog-AMS vs. SPICE view usage for robust AMS Verification of Power Management Controller and Mode Transition

The SOCs produced today provide a high level of functionality, driving a wide range of applications, while becoming more and more cost effective. This means that the complexity of the SOC too is ...
Electronic Design

Consolidation Looms In Verification

The year 2003 will see design teams shift from IC implementation to functional verification. The actual kickoff for this switch was at DAC 2002 in New Orleans, where Synopsys introduced an intelligent ...
Design-Reuse

NextOp Announces BugScope Assertion Synthesis for Progressive, Targeted Verification

SANTA CLARA, Calif., May 6, 2010 -- NextOp Software, Inc. today announced BugScope, the industry’s first assertion synthesis product to synthesize high quality assertions and functional coverage ...
EDN

Verilog-AMS vs. SPICE view: An SoC verification comparison

Dozens of analog and digital IP blocks are integrated into today’s SoCs. They contain multiple voltage domains that support several modes, like Standby, Low power, Reduced Clock Mode, etc.
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.