Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...

This Design Idea describes a new class of logic gates, which we have named resistor-FET-logic, aka “RFL.” How do we know it is new? While FET switches are common today, we have been unable to find a ...

Toshiba Corporation has launched a new series of CMOS multi-function gate logic devices that support 5V systems and that are housed in small packages suitable for mobile devices such as mobile phones, ...

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...