TechRepublic

Analysis of Different Bit Carry Look Ahead Adder Using Verilog Code

Adders are one of the widely used digital components in digital integrated circuit design. In this paper, various adder structures can be used to execute addition such as serial and parallel ...
EDN

Design of a FPGA Configurable Logic Block for minimum energy and delay

Complete Layout, Design and Optimization of a FPGA Configurable Logic Block for minimum energy and delay: The CLB can function as one 8-bit adder, two 4-bit adders, a subtractor, multiplier, counter ...
EDN

“Design and Simulation of an n-bit 3-Number Adder” (Using VHDL) (Nov-Dec 2009)

•The final design for a 16-bit 3 number adder resulted in a worst-case propagation delay (tpd) of 22.017ns with Speculative execution and a group size of 4, an 18.5% improvement from 26.772ns, without ...
Hackaday

2-bit Full Adder Using Just Thirty Six 555 Timers

This 2-bit adder was a lot of work to build. It uses a total of thirty-six 555 timers and it does have the option of adding or subtracting numbers. It’s a rather unorthodox use of the part, depending ...