News

Linux Journal

Icarus Verilog: Open-Source Verilog More Than a Year Later

About 16 months ago, in the February 2001 Linux Journal [see www.linuxjournal.com/article/4428], we reviewed the state of open source in electronic design automation ...
Hackaday

Open Source IDE For FPGAs As QtCreator Learns Verilog

Classic battles: PC vs Mac, Emacs vs Vi, Tastes Great vs Less Filling, and certainly one that we debate around the Hackaday watercooler: command line or IDE? There’s something to be said for using ...
Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...
Semiconductor Engineering

Open Verilog International

Open Verilog International (OVI) was founded in 1990 to support and extend the Verilog Hardware Description Language (HDL). It merged with VHDL International (VI) in 2000 to become Accellera. Verilog ...
Design-Reuse

System Verilog Assertions Simplified

Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains ...
Design-Reuse

System Verilog Macro: A Powerful Feature for Design Verification Projects

For any design verification (DV) project, following best coding practices make life easier for the teammates. On the other hand, bad coding style leads to a lot of issues when the code is reused, or ...