EDN

How to Read Data Sheets: Logic Timing (Part 3, Flip-Flops)

The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K = Reset) by interpreting the J = K = 1 condition as a “flip” or toggle command. In my previous column, we introduced latches and ...
EDN

SR Flip Flop Design with NOR Gate

Here is a simple circuit which helps to know how SR Flip Flop can be designed using NOR gate. In the circuit diagram, there are two input terminals S and R. The SR Flip Flop is one of the fundamental ...
Hackaday

Learn Flip Flops With Simulation

Digital design with combinatorial gates like AND, OR, and NOT gates is relatively straightforward. In particular, when you use these gates to form combinatorial logic, the outputs only depend on the ...
Embedded

Embedded system timing analysis basics: Part 1 – Timing is essential

Just as in comedy, timing is essential to the success of a microcomputer design. Often it is quite possible to get one system functioning by simply interconnecting the various compo­nents. But it is ...
Embedded

Using multi-bit flip-flop custom cells to achieve better SoC design efficiency

System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing ...