Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Nasdaq

Synopsys VCS Used by Graphcore to Verify Next-Generation Colossus GC200 IPU

MOUNTAIN VIEW, Calif., July 20, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Graphcore used the Synopsys VCS® simulation solution with Verdi® debug to verify its recently ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
Design-Reuse

Synopsys Integrates VERA and VCS to Boost Verification Performance

VCS Direct Kernel Interface, Coverage Engine Integration and Waveform Analysis Integration Raise Verification Performance and Productivity MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Nov. 12, 2001-- ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Nasdaq

Synopsys Collaborates with Google Cloud to Broadly Scale Cloud-based Functional Verification

MOUNTAIN VIEW, Calif., Sept. 9, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with Google Cloud to provide a full end-to-end solution to perform functional ...
Semiconductor Engineering

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism

Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User ...
Semiconductor Engineering

Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics

Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for ...
EDN

Speeding up simulation

EDA vendors may not want you to know about a paper from the recent Design and Verification Conference & Exhibition (DVCon) and available at the author's Web site. In it, Cisco Systems Inc. hardware ...