Design-Reuse

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
EDN

VHDL 101 – Introduction

Field-Programmable Gate Arrays (FPGAs) look like very complex integrated circuits. Performing bespoke functions and having engineers programming them in strange languages puts many people off. This is ...
Hackaday

FPGA Snake Game Uses No VHDL At All

We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES ...
insideHPC

FPGA Programming Made Easy

Field-programmable gate arrays (FPGAs) are becoming an increasingly popular tool for applications where high performance, low latency and power efficiency are requires. Since an FPGA can be ...
Semiconductor Engineering

AI Starting To Simplify Design Of Programmable Logic

Designing and deploying DSPs FPGAs aren’t the only programmable hardware option, or the only option challenged by AI. While AI makes it easier to design DSPs, there are rising complexities due to the ...
Yahoo Finance

Menta Follows FPGA Leaders by Selecting Verific for its SystemVerilog, VHDL Front End

ALAMEDA, CA--(Marketwired - Jul 2, 2014) - Verific Design Automation today announced Menta® selected its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers to serve as the front end to ...
Design-Reuse

PROGRAMMABLE LOGIC: Compiler turns FPGAs into supercomputers

Santa Cruz, Calif. — Scientists, engineers and software developers who know nothing about chip design can now compile high-performance computing applications into FPGAs, according to startup ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...