EDN

Design planning for large SoC implementation at 40nm – Part 2

Die size and power estimations are at the foundation of SoC implementation. The key is how early and how accurately can it be done. These two parameters are the main data point for making some ...
EDN

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the ...
Electronic Design

Solutions Mitigate Mixed-Signal SoC Implementation Headaches

The concept of silicon realization, as defined in the Cadence EDA360 vision paper, represents everything required to produce a system-on-a-chip (SoC) design in silicon. 1 Silicon realization addresses ...