EDN

Instruction Set Architecture

Instruction Set Architecture (ISA) is a set of instructions defined for the processor’s architecture. These are the instructions that the processor understands. It defines the hardware and software ...
EDN

Evolving a classic RISC architecture

MIPS Technologies released details this week of the latest incarnation of the architecture that defined RISC at a time when the rest of the industry was fully engaged in CISC architecture processors.
Semiconductor Engineering

How To Extend The ‘Unscalable’ RISC Architectures

A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled RISC Is Fundamentally Unscalable. This blog was really quite interesting and made some very ...
CNET

AMD's SSE5 ends the old RISC vs. CISC debate

Prompted by the chipmaker's announcement of the SSE5 instruction-set extensions, Glaskowsky analyzes the ultimate outcome to this old controversy. Peter N. Glaskowsky is a computer architect in ...
ExtremeTech

RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source

A new instruction set by the original creator of MIPS aims to reinvent the ultra-low power, high-efficiency processor -- and to do so with an architecture that's fundamentally open and available to ...
TechRepublic

Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and X86 Architectures

RISC vs. CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape. Today, energy ...
Design-Reuse

How to extend the ‘unscalable’ RISC architectures

A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled, RISC Is Fundamentally Unscalable. This blog was really quite interesting and made some very ...