While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

“Golden” RTL code has been seen as a holy grail of IC design for many years. It promises to deliver code that is reusable in future designs. However, golden RTL is very difficult to achieve. Too many ...

Mitigating LLM Memorization in RTL Code Generation Against IP Leakage” was published by researchers at University of Central ...

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool ...

Expanding predictive analysis technology into the functional space, the Periscope functional analysis tool helps engineers quickly determine whether their RTL design descriptions are functionally ...

Preparing a design for reuse, especially one not originally written with reuse in mind, often requires changing the RTL. Ideally, these changes should be made as quickly as possible and without ...