EDN

Optimizing loop filter bandwidth for modulated PLL ramping waveforms

There are two common architectures for radar. The first architecture, shown in Figure 1, uses a digital-to-analog converter (DAC) to tune the frequency of a voltage-controlled oscillator (VCO) in ...
Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, ...
Electronics Weekly

Analogue or digital in PLL design

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...
Design-Reuse

Ultra Low Jitter Wide Band LC PLL

The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for current and next generation SerDes transceivers. Not only must they handle multiple ...
Design-Reuse

Selecting PLLs for ASIC Applications requires tradeoffs

Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come ...
EDN

SOC-PLL design requires trade-offs

PLLs (phase-locked loops) are common analogcircuits in SOCs (systems on chips). Almost allSOCs with a clock rate greater than 30 MHzuse a PLL for frequency synthesis. However, a“one-size-fits-all” PLL ...