Communicationbetween processors and memories is often a major bottleneck, making the designof the memory controller a critical task in determining overall system-levelperformance. The memory ...

If you want to know why Intel doesn't include a memory controller on its chips, you've got at a lot of factors, according to Intel CEO Paul Otellini. A memory controller is a small piece of ...

The number of SoCs that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to DDR SDRAM interfaces such as DDR, DDR2, and DDR3 to address their ...

To see how a one-chip memory controller can meet practical size, performance, and cost specifications, consider an embedded system built around a 33-MHz i960CF µP (Fig 2). This 33-MHz, 32-bit RISC µP ...