EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Design-Reuse

CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core

January 9, 2023 - Global IP Core Sales - The new CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding different code rates (i.e., ...
Design-Reuse

DVB-T2 Demodulator + Decoder LDPC/ BCH IP Core Available For Immediate Implementation From Global IP Core

March 7, 2023 - Global IP Core Sales - The new DVB-T2 demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to ...
Nature

LDPC Decoding Algorithms on Graphics Processing Units

Low-density parity-check (LDPC) codes represent one of the most effective error-correcting schemes available, approaching Shannon’s theoretical limit whilst maintaining a relatively low decoding ...
New Electronics

AccelerComm develops LDPC Decoder for Intel’s FlexRAN

AccelerComm, the company specialising in optimisation and latency reduction IP, has announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The solution is ...
Total Telecom

AccelerComm’s New Highly Optimised LDPC Decoder in Software for Intel’s FlexRAN Reference Software Will Increase 5G Throughput by up to 3X

AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, today announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...
Electronic Design

Flash Controllers Get Better Efficiency With Low Density Parity Check (LDPC)

What does satellite communication and flash storage have in common? They are error prone and low density parity check (LDPC) code technology is the answer to the ...
insideHPC

AccelerComm Unveils Integrated PUSCH Decoder for 5G NR

Southampton, UK and MWC Shanghai, China – 18 th February 2020: AccelerComm, the channel coding specialist, has announced Physical Layer IP for 5G NG designed to increase spectral efficiency and reduce ...
Semiconductor Engineering

The Week In Review: Design

Altium released the latest version of its PCB design suite. Improvements include a new interface and an upgrade to 64-bit architecture combined with multi-threaded task optimizations. Other additions ...
Total Telecom

AccelerComm Unveils Fully Integrated PUSCH Decoder to Supercharge 5G NR for Performance-Critical Channels

AccelerComm, the channel coding specialist, is supercharging 5G NR with cutting edge Physical Layer IP which increases spectral efficiency and reduces latency. The company today announced a complete ...