Semiconductor Engineering

Dual Instruction-Set Architecture, Supporting A TTA And RISC-V Instruction Set Via a Lightweight Microcode Hardware Unit

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...
Electronic Design

RISC-V: The Instruction-Set Alternative

First and foremost, RISC-V is a modular, open-source, instruction set definition and nothing more. RISC-V as an ecosystem is much more. The instruction set provides the encoding and semantics, but it ...
inc42

What Is Chip Architecture? Here’s All You Need to Know

In semiconductors, architecture refers to the instruction set architecture (ISA), a detailed set of rules and specifications governing how a chip processes data and executes instructions. This ISA ...
SiliconANGLE

Arm moves to cancel Qualcomm’s instruction set architecture license

Arm Holdings plc plans to cancel a license that gives Qualcomm Inc. permission to use its instruction set architecture in chips. Bloomberg reported the development today. Qualcomm, the world’s top ...
AppleInsider

Apple investigating RISC-V instruction set architecture, job listing shows

A job listing posted to Apple's website this week reveals the company is researching RISC-V instruction set architecture solutions, suggesting future in-house chip designs might implement the ...
Semiconductor Engineering

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)

A new technical paper titled “Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions” was published by researchers at Tampere University. Abstract “Custom instruction ...
SiliconANGLE

Intel and AMD team up to improve the x86 processor architecture

Intel Corp. and Advanced Micro Devices Inc. today launched an industry group dedicated to improving the x86 instruction set architecture. Besides the two chipmakers, the consortium, announced at the ...
TechSpot

Intel AVX10, APX are the next step in the x86 instruction set evolution

Why it matters: Intel is gearing up for what the company considers the "next major step" in the evolution of the original x86 instruction set architecture (ISA). The Santa Clara corporation is ...
Hackaday

Checking In On The ISA Wars And Its Impact On CPU Architectures

An Instruction Set Architecture (ISA) defines the software interface through which for example a central processor unit (CPU) is controlled. Unlike early computer systems which didn’t define a ...
Electronic Design

Embracing Multicore and RISC-V Architectures in SoC Design

Discover the advantages of the open-source RISC-V architecture in promoting efficiency and innovation in semiconductor design. Learn how RISC-V facilitates the development of multicore SoC designs ...
9to5Mac

Apple exploring open-source RISC-V chips, but almost certainly not instead of ARM

An Apple job ad reveals that the company is exploring the use of RISC-V chips, an open-source processor tech that competes with the ARM architecture used for Apple’s A-series and M-series chips.