An appendix covers how to write your own operating system for RISC-V in about 1,000 lines of code. Don’t speak Japanese? An English version is available free on the Web and on GitHub.

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero ...

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing ...

Western Digital has announced that it's completed work on its "Swerv" RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design.

By contributing the FE310 RTL code to the open source community, SiFive aims to encourage open source development of both software support for RISC-V as well as hardware development.