EDN

Hierarchical physical design—issues and methodologies

In IC physical design, there is a tendency to focus on the synthesis and layout tasks, and to not give much consideration to the chip finishing tasks, at least not until the more pressing matters of ...
Semiconductor Engineering

Efficient Hierarchical Verification For Low Power Designs

Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, ...
Design-Reuse

NEC Develops Novel Design Method for Large Scale & High Speed LSI with More than 50 Million Transistors

Tokyo -- August 31, 2006-- NEC Corporation (NEC) and NEC Electronics Corporation (NEC Electronics) announced that they have succeeded in the development of a new design method for large-scale ...
EDN

Synopsys Takes Hierarchical Timing Signoff Mainstream

Hierarchical timing reuse reduces schedule-risk while using fewer compute resources Automated distribution of full-chip analysis runs on smaller, more readily available resources Dynamic top-down and ...