EDN

SunaptiCAD VeriLogger Extreme: Verilog 2001 simulator provides faster RTL and gate-level simulations

Reducing simulation debugging time, the compiled-code Verilogger Extreme Verilog 2001 simulator provides fast simulation of RTL and gate-level simulations using SDF (Synopsys Delay Format) timing ...
Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Fifteen years ago verification of FPGA designs was easy but as the size of FPGAs has increased so have the verification challenges, Jerry Kaczynski explains. Today it is not unusual for FPGA users to ...
Business Wire

Aldec® Delivers $1,995 Mixed Language Simulator to FPGA Market

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a leader in RTL simulation and Electronic Design Automation (EDA), unveils a new low-cost mixed language RTL simulator -- Active-HDL™ Designer Edition.
Semiconductor Engineering

Hybrid Emulation

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for Cadence; Russ ...
New Electronics

Aldec fpga simulation technology added to Altium Designer

Altium and Aldec have signed an OEM agreement that adds Aldec's fpga simulation capabilities to Altium Designer. The agreement adds an extra dimension for electronics designers working with fpgas and ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Design-Reuse

Advantages of FPGA design methodologies

Once used only for glue logic, FPGAs have progressed to a point where system-on-chip (SoC) designs can be built on a single device. The number of gates and features has increased dramatically to ...
Design-Reuse

OneSpin Announces Immediate Availability of OneSpin 360 EC-FPGA Tool Qualification Kit Certified for ISO 26262, IEC 61508, EN 50128

MUNICH and SAN JOSE, CALIF. – February 14, 2018 – OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), announced immediate ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
EDN

FPGA users taxed but satisfied

FPGA design is getting more complex and is demanding sophisticated EDA tools, according to the EE Times/Deutsche Bank 2005 EDA survey. But the 116 FPGA designers who responded to the survey generally ...