The 4Kp30 multi-sensor camera reference design is by Altera and designed for its Agilex 5 FPGAs. It uses industry-standard MIPI connectivity: D-PHY and MIPI CSI-2 for the FPGA interface and Altera’s ...

Developed with Xilinx' Premier Alliance members Northwest Logic and Xylon, the low cost Xilinx FPGA-based MIPI interface IP is optimized for cost sensitive video displays and cameras. The company’s ...

Mixel’s MIPI PHY IP integrated into the HME-H3 FPGA, the industry’s first FPGA to support MIPI C-PHY v2.0 San Jose, CA – April 18, 2023 - Mixel ®, Inc. (Mixel), a leading provider of mixed-signal ...

SAN JOSE, Calif., Sept. 8, 2014-- Xilinx, Inc. (NASDAQ: XLNX) and Northwest Logic and Xylon, Xilinx Premier Alliance Members, announce the availability of a low cost Xilinx FPGA-based MIPI interface ...

Arasan announces the immediate availability of its MIPI CSI IP supporting C-PHY v2.0 speeds of up to 54.72Gbps (when operating up to 8 Gsps with all 3 channels) for FPGA designs SAN JOSE, Calif., Nov.

SAN JOSE, Calif.--(BUSINESS WIRE)--Mixel ®, a leading provider of mixed-signal intellectual property (IP), and Hercules Microelectronics (HME), a China-based developer of programmable FPGA cores, ...

A test chip incorporating Mixel’s MIPI C-PHY/D-PHY combo IP has been manufactured on STMicroelectronics’ 40-nm low-power process technology and it has been a first-time silicon success. Other MIPI IP ...

Achieving higher resolution is a never-ending race for camera, TV and display manufacturers. After the emergence of 4K ultra high definition (Ultra HD) imaging in the market, it became the main ...

Lattice Semiconductor’s CrossLinkPlus is designed to handle interface conversion, including support for MIPI virtual channels (Fig. 1). The chip will be useful to bridge between a peripheral’s ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Mixel ®, a leading provider of mixed-signal intellectual property (IP), announced today that Mixel’s MIPI ® IP solution has been successfully integrated into Lattice ...