Semiconductor Engineering

Making Cache Coherent SoC Design Easier with Ncore

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris ...
Semiconductor Engineering

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and ...
Design-Reuse

ArterisIP Advances Machine Learning SoC Design with Ncore 2.0 Cache Coherent Interconnect and Resilience Package

SoC interconnect IP enables highly scalable neural network systems with integrated hardware functional safety features for ISO 26262 ASIL D compliance Linley Autonomous Hardware Conference 2017, SANTA ...
Design-Reuse

Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and ...