Semiconductor Engineering

Making Cache Coherent SoC Design Easier with Ncore

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris ...
Semiconductor Engineering

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and ...
Design-Reuse

Modular Design Of Level-2 Cache For Flexible IP Configuration

The microprocessor-memory gap has been growing for over 30 years, and in that time caches have been crucial components in digital system design. All high-performance microprocessors are designed with ...