The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...

Memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to meet ...

With the move to advanced process technologies, concerns over device power once largely limited to specialized markets have escalated rapidly among mainstream designers. More semiconductor companies ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...

Representatives of Cadence Design Systems’ (www.cadence.com) design-for-test group were on hand at the Design Automation Conference (held June 7-10 in San Diego, CA) to describe bringing timing to the ...

The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are ...

Automotive integrated circuits (ICs) are the critical drivers behind modern vehicle automation, safety, and efficiency. As electronic systems in automobiles become increasingly complex, robust testing ...

Join us on Wednesday, December 15 at noon Pacific for the Design for Test Hack Chat with Duncan Lowder! If your project is at the breadboard phase, or even if you’ve moved to a PCB prototype, it’s ...