Electronic Design

Signoff Evolves From Design-Rule Checking To Yield Analysis

IC designers are a lucky bunch. Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple ...
Semiconductor Engineering

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design

As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts.
EDN

New error comparison scheme proposed for design rule checking flows

BENGALURU, India — With design rule checking becoming hugely complex in the deep sub-micron regime, there is a large run time for physical verification tools, for the number of design rules that must ...
Business Wire

Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corporation (NASDAQ:MENT) today announced the release of a major new product in the HyperLynx® suite, the market-leading, high-speed analysis ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
EDN

A primer on logical equivalence checking (LEC) using Conformal

Designing a chip is a complex process. It starts with defining the architectural requirements, then microarchitecture development, followed by RTL design and functional verification. Then the design ...
Nasdaq

ASE launches its Integrated Design EcosystemTM to enable silicon package design efficiencies that reduce cycle time by half

SUNNYVALE, Calif.--(BUSINESS WIRE)-- Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced the launch of its Integrated ...
Design-Reuse

Aldec adds Documentation for Safety-Critical Designs in ALINT 2012.01

Henderson, NV – January 23, 2012 – Aldec, Inc., announces the release of ALINT 2012.01,a design rule checking application for HDL-based FPGA/ASIC designs. The new release adds documentation ...