As semiconductor technology pushes the boundaries of scale and complexity, traditional VLSI physical design methodologies are struggling to keep pace. The rise of Artificial Intelligence (AI), ...

A new technical paper titled “Multimodal Chip Physical Design Engineer Assistant” was published by researchers at National Taiwan University, University of California, Los Angeles and NVIDIA Research.

EDA company’s clients have finished hundreds of new tapeouts using Cadence Cerebrus AI to speed development and make chips that run faster, use less energy, and cost less. For Cadence, AI is all about ...

Artificial intelligence chip startup SiMa Technologies Inc. today announced it’s shipping its second-gen system-on-chip platform specifically designed for multimodal physical AI workloads. The new ...

Synopsys is seeing strong demand for its newer AI technologies in test, verification, manufacturing and analog migration, in addition to the ongoing need for design optimization (DSO.ai). Synopsys was ...

Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp ...

IROC Technologies was tasked by the European Space Agency (ESA) to assess the suitability of Ultra Deep Submicron (UDSM) technology nodes below 22 nm for space applications. IROC set out to build a ...