The dividing lines between system buses, system intraconnects, and system interconnects are getting more blurry all the time. And that is, oddly enough, going to turn out to be a good thing in the ...

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...

In the selection and qualification process for semiconductor IP, design teams often consider the cost of in-house development. Network-on-Chip (NoC) IP is no different. In “When Does My SoC Design ...

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.

A new technical paper titled “WARDen: Specializing Cache Coherence for High-Level Parallel Languages” was published by researchers at Northwestern University and Carnegie Mellon University.

This Application Note explores the implications associated with performing Direct Memory Access (DMA) operations on an ARM multi-core system such as the ARM11 MPCore and Cortex-A9 MPCore. The target ...