Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
EDN

Driving CMOS totem poles with logic signals, AC coupling, and grounded gates

Despite massive, large-scale integration being ubiquitous in contemporary electronic design, discrete MOSFETs in the classic CMOS totem pole topology are still sometimes indispensable. This makes tips ...
EDN

Gate driver boosts reliability in high-power designs

Featuring 2.5-kV capacitive isolation, the Littelfuse IX3407B gate driver improves signal integrity and safety in power ...
Electronic Design

It’s Hot, Powering, And Burning CMOS Logic Circuits

Fig 1. A typical CMOS input circuit comprises a “P” and “N” transistor. One is fully “on” for logic high, and the other is “on” for a logic low. Fig 2. When a CMOS input pin is at logic high or low ...
Nature

Wide Fan-In Domino Logic Circuits in CMOS Technology

The rapid evolution of CMOS technology has driven the need for more efficient and high-speed logic circuits, with wide fan-in domino logic circuits emerging as a promising solution. These circuits, ...