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A tiny firm wants to slash energy consumption by changing the way CPUs are designed - and it is even planning a new high performance server chip

NeoLogic raises $10 million to advance CMOS+ CPUs, reducing circuit complexity CMOS+ enables 6-32 input gates, reducing power use and die size First processors expected in 2026, targeting energy ...
SiliconANGLE

NeoLogic raises $10M to develop power-efficient server processors

NeoLogic Ltd., a startup that hopes to make processors more efficient by reducing their transistor counts, has raised $10 million in funding. The company announced the Series A round today. It ...
insideHPC

Diraq Says It Drives 2-Qubit Gate Accuracy in CMOS above 99%

SYDNEY, AUSTRALIA – AUGUST 20, 2024 – Quantum computing company Diraq announced it has demonstrated consistent and repeatable operation with above 99 percent fidelity of two-qubit gates in the SiMOS ...
Electronic Design

So...The CMOS Circuits in Our Texts Go Back to 1963?

The first CMOS chip was created by Fairchild Semiconductor, presented at ISSCC in 1963. The logic topologies used in today’s textbooks originated in this work. P-type devices are slower than N-type by ...